1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to resistors provided in the semiconductor layer in complex integrated circuits.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors and resistors, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
Although transistor elements are the dominant circuit element in highly complex integrated circuits which substantially determine the overall performance of these devices, other components, such as capacitors and resistors, may be required, wherein the size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area. Moreover, the passive circuit elements, such as the resistors, may have to be provided with a high degree of accuracy in order to meet tightly set margins according to the basic circuit design. For example, even in substantially digital circuit designs, corresponding resistance values may have to be provided within tightly set tolerance ranges so as to not unduly contribute to operational instabilities and/or enhanced signal propagation delay. For example, in sophisticated applications, resistors may frequently be provided in the form of “integrated polysilicon” resistors which may be formed above the semiconductor layer and/or respective isolation structures so as to obtain the desired resistance value without significantly contributing to parasitic capacitance, as may be the case in “buried” resistive structures which may be formed within the active semiconductor layer. A typical polysilicon resistor may, thus, require the deposition of the basic polysilicon material, which may frequently be combined with the deposition of a polysilicon gate electrode material for the transistor elements. During the patterning of the gate electrode structures, the resistors may also be formed, the size of which may significantly depend on the basic specific resistance value of the polysilicon material and the subsequent type of dopant material and concentration that may be incorporated into the resistors to adjust the resistance values.
Due to the ongoing shrinkage of the critical dimensions of transistors, sophisticated materials for the corresponding gate electrode structures may be used, such as high-k dielectric materials for the gate insulation layers, in combination with non-polysilicon materials, such as metal-containing materials, thereby typically requiring sophisticated manufacturing regimes. For example, frequently, the deposition of a polysilicon material may no longer be required for providing sophisticated gate electrode structures so that the formation of corresponding polysilicon resistors above the basic semiconductor material may be associated with additional deposition processes, which in turn may not be compatible with the sophisticated manufacturing strategies in forming high-k metal gate electrode structures or which may at least contribute to a significant additional complexity or at least reduced flexibility of the entire manufacturing flow.
On the other hand, providing buried resistors, which may typically be formed below respective active regions of transistor elements and the like or which may be formed in the basic semiconductor material in dedicated resistor regions, may have an increased parasitic capacitance due to any adjacent semiconductor materials or active regions, thereby contributing to increased signal propagation delay, which may frequently not be compatible with device requirements of sophisticated semiconductor devices, in which high-k metal gate electrode structures may be implemented in order to enhance overall device performance. That is, combining conventional buried resistor structures, which may typically be associated with a high parasitic capacitance with sophisticated transistor elements based on non-polysilicon gate electrode materials, may be less than desirable in view of overall device performance.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.